Flatness & Nanotopography -- Description
With the implementation of CMP planarization processes for Shallow Trench Isolation1, the nanotopography of the silicon wafer is becoming a more significant factor to consider. Nanotopography is defined as "the deviation of a surface within a spatial wavelength of around 0.2 to 20 mm."2 This is a parameter that measures the front-surface, free-state topology of an area which can range in size from fractions of a millimeter to tens of millimeters. In this sense, nanotopography differs from front-referenced site flatness in that for nanotopography the wafer is measured in a free state, while for flatness it is referenced to a flat chuck. A wafer may have perfect flatness (in the classical definition of flatness), yet still have nanotopography. If a wafer has surface irregularities on the front and backside of the wafer, but front and back surfaces are parallel, the wafer has perfect flatness. However, the same wafer will exhibit nanotopography (Figure 1). Nanotopography bridges the gap between roughness and flatness in the topology map of wafer surface irregularities in spatial frequency (Figure 2). As linewidths shrink, with non-uniform pattern density and with the use of hard pads for CMP, nanotopography may significantly degrade in dielectric film uniformity3,4.

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